数字逻辑基础与Verilog设计【2025|PDF下载-Epub版本|mobi电子书|kindle百度云盘下载】

数字逻辑基础与Verilog设计PDF格式电子书版下载

注意：本站所有压缩包均有解压码： 点击下载压缩包解压工具

Chapter 1 DESIGN CONCEPTS1

1.1 Digital Hardware2

1.1.1 Standard Chips4

1.1.2 Programmable Logic Devices4

1.1.3 Custom-DesignedChips5

1.2 The Design Process6

1.3 Design of Digital Hardware8

1.3.1 Basic Design Loop8

1.3.2 Design of a Digital Hardware Unit9

1.4 Logic Circuit Design in This Book11

1.5 Theory and Practice14

References15

Chapter 2 INTRODUCTION TO LOGIC CIRCUITS17

2.1 Variables and Functions18

2.2 Inversion21

2.3 Truth Tables22

2.4 Logic Gates and Networks23

2.4.1 Analysis of a Logic Network24

2.5 Boolean Algebra27

2.5.1 The Venn Diagram30

2.5.2 Notation and Terminology34

2.5.3 Precedence of Operations34

2.6 Synthesis Using AND,OR,and NOT Gates35

2.6.1 Sum-of-Products and Product-of-Sums Forms37

2.7 NAND and NOR Logic Networks41

2.8 Design Examples44

2.8.1 Three-Way Light Control44

2.8.2 Multiplexer Circuit45

2.9 Introduction to CAD Tools48

2.9.1 Design Entry48

2.9.2 Synthesis51

2.9.3 Functional Simulation52

2.9.4 Summary52

2.10 Introduction to Verilog54

2.10.1 Structural Specification of Logic Circuits55

2.10.2 Behavioral Specification of Logic Cirucits58

2.10.3 How Not to Write Verilog Code60

2.11 Concluding Remarks60

Problems61

References65

Chapter 3 IMPLEMENTATION TECHNOLOGY67

3.1 Transistor Switches69

3.2 NMOS Logic Gates71

3.3 CMOS Logic Gates74

3.3.1 Speed of Logic Gate Circuits81

3.4 Negative Logic System82

3.5 Standard Chips83

3.5.1 7400-Series Standard Chips83

3.6 Programmable Logic Devices87

3.6.1 Programmable Logic Array(PLA)87

3.6.2 Programmable Array Logic(PAL)90

3.6.3 Programming of PLAs and PALs92

3.6.4 Complex Programmable Logic Devices(CPLDs)94

3.6.5 Field-Programmable Gate Arrays98

3.6.6 Using CAD Tools to Implement Circuits in CPLDs and FPGAs102

3.7 Custom Chips,Standard Cells,and Gate Arrays103

3.8 Practical Aspects106

3.8.1 MOSFET Fabrication and Behavior106

3.8.2 MOSFET On-Resistance110

3.8.3 Voltage Levels in Logic Gates111

3.8.4 Noise Margin113

3.8.5 Dynamic Operation of Logic Gates114

3.8.6 Power Dissipation in Logic Gates117

3.8.7 Passing Is and Os Through Transistor Switches118

3.8.8 Fan-in and Fan-out in Logic Gates120

3.9 Transmission Gates126

3.9.1 Exclusive-OR Gates127

3.9.2 Multiplexer Circuit128

3.10 Implementation Details for SPLDs,CPLDs,and FPGAs129

3.10.1 Implementation in FPGAs135

3.11 Concluding Remarks137

Problems138

References147

Chapter 4 OPTIMIZED IMPLEMENTATION OF LOGIC FUNCTIONS149

4.1 Kamaugh Map150

4.2 Strategy for Minimization158

4.2.1 Terminology159

4.2.2 Minimization Procedure160

4.3 Minimization of Product-of-Sums Forms164

4.4 Incompletely Specified Functions166

4.5 Multiple-Output Circuits167

4.6 Multilevel Synthesis171

4.6.1 Factoring172

4.6.2 Functional Decomposition175

4.6.3 Multilevel NAND and NOR Circuits181

4.7 Analysis of Multilevel Circuits184

4.8 Cubical Representation189

4.8.1 Cubes and Hypercubes189

4.9 A Tabular Method for Minimization193

4.9.1 Generation of Prime Implicants193

4.9.2 Determination of a Minimum Cover195

4.9.3 Summary of the Tabular Method200

4.10 A Cubical Technique for Minimization201

4.10.1 Determination of Essential Prime Implicants204

4.10.2 Complete Procedure for Finding a Minimal Cover206

4.11 Practical Considerations208

4.12 CAD Tools209

4.12.1 Logic Synthesis and Optimization210

4.12.2 Physical Design211

4.12.3 Timing Simulation213

4.12.4 Summary of Design Flow213

4.12.5 Examples of Circuits Synthesized from Verilog Code216

4.13 Concluding Remarks220

Problems221

References226

Chapter 5 NUMBER REPRESENTATION AND ARITHMETIC CIRCUITS229

5.1 Positional Number Representation230

5.1.1 Unsigned Integers230

5.1.2 Conversion Between Decimal and Binary Systems231

5.1.3 Octal and Hexadecimal Representations232

5.2 Addition of Unsigned Numbers234

5.2.1 Decomposed Full-Adder238

5.2.2 Ripple-Carry Adder239

5.2.3 Design Example240

5.3 Signed Numbers240

5.3.1 Negative Numbers240

5.3.2 Addition and Subtraction244

5.3.3 Adder and Subtractor Unit248

5.3.4 Radix-Complement Schemes249

5.3.5 Arithmetic Overflow253

5.3.6 Performance Issues254

5.4 Fast Adders255

5.4.1 Carry-Lookahead Adder255

5.5 Design of Arithmetic Circuits Using CAD Tools262

5.5.1 Design of Arithmetic Circuits Using Schematic Capture262

5.5.2 Design of Arithmetic Circuits Using Verilog265

5.5.3 Using Vectored Signals268

5.5.4 Using a Generic Specification269

5.5.5 Nets and Variables in Verilog270

5.5.6 Arithmetic Assignment Statements271

5.5.7 Representation of Numbers in Verilog Code275

5.6 Multiplication277

5.6.1 Array Multiplier for Unsigned Numbers279

5.6.2 Multiplication of Signed Numbers279

5.7 Other Number Representations282

5.7.1 Fixed-Point Numbers282

5.7.2 Floating-Point Numbers282

5.7.3 Binary-Coded-Decimal Representation284

5.8 ASCII Character Code289

Problems291

References295

Chapter 6 COMBINATIONAL-CIRCUIT BUILDING BLOCKS297

6.1 Multiplexers298

6.1.1 Synthesis of Logic Functions Using Multiplexers303

6.1.2 Multiplexer Synthesis Using Shannou's Expansion304

6.2 Decoders311

6.2.1 Demultiplexers314

6.3 Encoders316

6.3.1 Binary Encoders316

6.3.2 Priority Encoders317

6.4 Code Converters318

6.5 Arithmetic Comparison Circuits320

6.6 Verilog for Combinational Circuits320

6.6.1 The Conditional Operator321

6.6.2 The If-Else Statement323

6.6.3 The Case Statement326

6.6.4 The For Loop331

6.6.5 Verilog Operators333

6.6.6 The Generate Construct338

6.6.7 Tasks and Functions339

6.7 Concluding Remarks343

Problems343

References347

Chapter 7 FLIP-FLOPS,REGISTERS,COUNTERS,AND A SIMPLE PROCESSOR349

7.1 BasicLatch351

7.2 Gated SR Latch353

7.2.1 Gated SR Latch with NAND Gates355

7.3 Gated D Latch356

7.3.1 Effects of Propagation Delays358

7.4 Master-Slave and Edge-Triggered D Flip-Flops359

7.4.1 Master-Slave D Flip-Flop359

7.4.2 Edge-Triggered D Flip-Flop360

7.4.3 D Flip-Flops with Clear and Preset362

7.5 T Flip-Flop364

7.5.1 Coufigurable Flip-Flops367

7.6 JK Flip-Flop367

7.7 Summary of Terminology368

7.8 Registers368

7.8.1 Shift Register369

7.8.2 Parallel-Access Shift Register370

7.9 Counters371

7.9.1 Asynchronous Counters371

7.9.2 Synchronous Counters374

7.9.3 Counters with Parallel Load378

7.10 Reset Synchronization378

7.11 Other Types of Counters382

7.11.1 BCD Counter382

7.11.2 Ring Counter383

7.11.3 Johnsou Counter384

7.11.4 Remarks on Counter Design385

7.12 Using Storage Elements with CAD Tools385

7.12.1 Including Storage Elements in Schematics385

7.12.2 Using Verilog Constructs for Storage Elements388

7.12.3 Blocking and Nou-blocking Assignments390

7.12.4 Non-blocking Assignments for Combinational Circuits394

7.12.5 Flip-Flops with Clear Capability395

7.13 Using Registers and Counters with CAD Tools396

7.13.1 Including Registers and Counters in Schematics396

7.13.2 Using Library Modules in Verilog Code399

7.13.3 Using Verilog Constructs for Registers and Counters400

7.14 Design Examples405

7.14.1 Bns Structure405

7.14.2 Simple Processor417

7.14.3 Reaction Tuner429

7.14.4 Register Transfer Level(RTL)Code433

7.15 Concluding Remarks434

Problems434

References442

Chapter 8 SYNCHRONOUS SEQUENTIAL CIRCUITS445

8.1 Basic Design Steps447

8.1.1 State Diagram447

8.1.2 State Table449

8.1.3 State Assignment449

8.1.4 Choice of Flip-Flops and Derivation of Next-State and Output Expressions451

8.1.5 Timing Diagram453

8.1.6 Summary of Design Steps454

8.2 State-Assignment Problem458

8.2.1 One-Hot Encoding460

8.3 Mealy State Model462

8.4 Design of Finite State Machines Using CAD Tools467

8.4.1 Verilog Code for Moore-Type FSMs467

8.4.2 Synthesis of Verilog Code468

8.4.3 Simulating and Testing the Circuit470

8.4.4 Alternative Styles of Verilog Code471

8.4.5 Summary of Design Steps When Using CAD Tools473

8.4.6 Specifying the State Assignment in Verilog Code474

8.4.7 Specification of Mealy FSMs Using Verilog475

8.5 Serial Adder Example477

8.5.1 Mealy-Type FSM for Serial Adder477

8.5.2 Moore-Type FSM for Serial Adder479

8.5.3 Verilog Code for the Serial Adder480

8.6 State Minimization486

8.6.1 Partitioning Minimization Procedure486

8.6.2 Incompletely Specified FSMs493

8.7 Design of a Counter Using the Sequential Circuit Approach495

8.7.1 State Diagram and State Table for a Modulo-8 Counter495

8.7.2 State Assignment496

8.7.3 Implementation Using D-Type Flip-Flops497

8.7.4 Implementation Using JK-Type Flip-Flops498

8.7.5 Example—A Different Counter502

8.8 FSM as an Arbiter Circuit505

8.8.1 Implementation of the Arbiter Circuit508

8.8.2 Minimizing the Output Delays for an FSM511

8.8.3 Summary511

8.9 Analysis of Synchronous Sequential Circuits512

8.10 Algorithmic State Machine(ASM)Charts516

8.11 Formal Model for Sequential Circuits519

8.12 Concluding Remarks521

Problems521

References525

Chapter 9 ASYNCHRONOUS SEQUENTIAL CIRCUITS527

9.1 Asynchronous Behavior528

9.2 Analysis of Asynchronous Circuits531

9.3 Synthesis of Asynchronous Circuits540

9.4 State Reduction553

9.5 State Assignment568

9.5.1 Transition Diagram571

9.5.2 Exploiting Unspecified Next-State Entries574

9.5.3 State Assignment Using Additional State Variables578

9.5.4 One-Hot State Assignment582

9.6 Hazards584

9.6.1 Static Hazards585

9.6.2 Dynamic Hazards590

9.6.3 Significance of Hazards592

9.7 A Complete Design Example592

9.7.1 The Vending-Machine Controller592

9.8 Concluding Remarks599

Problems599

References604

Chapter 10 DIGITAL SYSTEM DESIGN605

10.1 Building Block Circuits606

10.1.1 Flip-Flops and Registers with Enable Inputs606

10.1.2 Shift Registers with Enable Inputs607

10.1.3 Static Random Access Memory(SRAM)609

10.1.4 SRAM Blocks in PLDs611

10.2 Design Examples612

10.2.1 A Bit-Counting Circuit612

10.2.2 ASM-Chart-Implied Timing Information613

10.2.3 Shift-and-Add Multiplier618

10.2.4 Divider623

10.2.5 Arithmetic Mean631

10.2.6 Sort Operation641

10.3 Clock Synchronization653

10.3.1 Clock Skew653

10.3.2 Flip-Flop Timing Parameters655

10.3.3 Asynchronous Inputs to Flip-Flops656

10.3.4 Switch Debouncing657

10.4 Concluding Remarks659

Problems659

References663

Chapter 11 TESTING OF LOGIC CIRCUITS665

11.1 Fault Model666

11.1.1 Stuck-at Model666

11.1.2 Single and Multiple Faults667

11.1.3 CMOS Circuits667

11.2 Complexity of a Test Set667

11.3 Path Sensitizing669

11.3.1 Detection of a Specific Fault671

11.4 Circuits with Tree Structure673

11.5 Random Tests674

11.6 Testing of Sequential Circuits677

11.6.1 Design forTestability677

11.7 Built-in Self-Test681

11.7.1 Built-in Logic Block Observer685

11.7.2 Signature Analysis687

11.7.3 Boundary Scan688

11.8 Printed Circuit Boards688

11.8.1 Testing of PCBs690

11.8.2 Instrumentation691

11.9 Concluding Remarks692

Problems692

References695

Appendix A VERILOG REFERENCE697

A.1 Documentation in Verilog Code699

A.2 White Space699

A.3 Signals in Verilog Code699

A.4 Identifier Names699

A.5 Signal Values,Numbers,and Parameters700

A.6 Net and Variable Types701

A.6.1 Nets701

A.6.2 Variables702

A.6.3 Memories703

A.7 Operators703

A.8 VerilogModule705

A.9 Gate Instantiations706

A.10 Concurrent Statements708

A.10.1 Continuous Assignments709

A.10.2 Using Parameters710

A.11 ProceduralStatements711

A.11.1 AlwaysandInitialBlocks711

A.11.2 The If-Else Statement713

A.11.3 Statement Ordering714

A.11.4 The Case Statement715

A.11.5 CasexandCasezStatements717

A.11.6 Loop Statements717

A.11.7 Blocking versus Non-blocking Assignments for Combinational Circuits721

A.12 Using Subeircuits721

A.12.1 Subcircuit Parameters723

A.12.2 Verilog 2001Generate Capability725

A.13 Functions andTasks726

A.14 Sequential Circuits730

A.14.1 AGatedDLateh730

A.14.2 DFlip-Flop730

A.14.3 Flip-Flops with Reset731

A.14.4 Instantiating a Flip-Flop from a Library732

A.14.5 Registers733

A.14.6 Shift Registers734

A.14.7 Counters735

A.14.8 An Example of a Sequential Circuit736

A.14.9 Moore-Type Finite State Machines737

A.14.10 Mealy-Type Finite State Machines739

A.15 Guidelines forWriting Verilog Code742

A.16 MAX+PlusⅡ Verilog Support745

A.16.1 Limitations in MAX+PlusⅡ745

A.17 Concluding Remarks746

References746

Appendix B TUTORIAL1747

B.1 Introduction748

B.1.1 Getting Started748

B.2 Design Entry Using Schematic Capture751

B.2.1 Specifying the Project Name752

B.2.2 Using the Graphic Editor752

B.2.3 Synthesizing a Circuit from the Schematic758

B.2.4 Performing Functional Simulation759

B.2.5 Using the Message Processor to Locate and Fix Errors763

B.3 Design Entry Using Verilog765

B.3.1 Specifying the Project Name765

B.3.2 Using the Text Editor765

B.3.3 Synthesizing a Circuit from the Verilog Code767

B.3.4 Performing Functional Simulation767

B.3.5 Using the Message Processor to Debug Verilog Code768

B.4 Design Entry Using Truth Tables768

B.4.1 Using the Waveform Editor769

B.4.2 Create the Timing Diagram769

B.4.3 Synthesizing a Circuit from the Waveforms770

B.5 Mixing Design-Entry Methods772

B.5.1 Creating a Schematic that Includes a Truth Table772

B.5.2 Synthesizing and Simulating a Circuit from the Schematic774

B.5.3 Using the Hierarchy Display775

B.5.4 Concluding Remarks775

Appendix C TUTORIAL2777

C.1 Implementing a Circuit in a MAX 7000 CPLD778

C.1.1 Using the Compiler779

C.1.2 Selecting a Chip780

C.1.3 Viewing the Logic Synthesis Options781

C.1.4 Examining the Implemented Circuit782

C.1.5 Running the Timing Simulator783

C.1.6 Using the Floorplan Editor784

C.2 Implementing a Circuit in a FLEX 10K FPGA787

C.3 Downloading a Circuit into a Device789

C.4 Making Pin Assignments790

C.4.1 Assigning Signals to Pins in the Floorplan Editor792

C.4.2 Making Pin Assignments Permanent794

C.5 Concluding Remarks795

Appendix D TUTORIAL 3797

D.1 Design Using Verilog Code798

D.1.1 The Ripple-Carry Adder Code798

D.1.2 Using the Timing Analyzer Module801

D.2 Using an LPM Module802

D.3 Design of a Sequential Circuit806

D.3.1 Using the Graphic Editor806

D.3.2 Synthesizing a Circuit and Using the Timing Simulator812

D.3.3 Using the Timing Analyzer813

D.3.4 Using Verilog Code814

D.4 Design of a Finite State Machine815

D.4.1 Implementation in a CPLD815

D.4.2 Implementation in an FPGA816

D.5 Concluding Remarks819

Appendix E COMMERCIAL DEVICES821

E.1 Simple PLDs822

E.1.1 The 22V10 PAL Device822

E.2 Complex PLDs824

E.2.1 Altera MAX 7000825

E.3 Field-Programmable Gate Arrays826

E.3.1 Altera FLEX 10K827

E.3.2 Xilinx XC4000830

E.3.3 Altera APEX 20K831

E.3.4 Altera Stratix832

E.3.5 Xilix Virtex834

E.4 Transistor-Transistor Logic835

E.4.1 TTL Circuit Families836

References837

INDEX838